One or more embodiments relate to a nonvolatile memory device and, more particularly, to a page buffer circuit configured to control the program speed by checking the threshold voltage of a cell more accurately through a double verification operation using an analog method, a nonvolatile memory device including the page buffer circuit, and a method of operating the nonvolatile memory device.
A NAND flash memory device (i.e., a type of a nonvolatile memory device) includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes word lines extending in rows, bit lines extending in columns, and cell strings corresponding to the respective bit lines.
The row decoder coupled to a string selection line, the word lines, and a common source line is placed on one side of the memory cell array. The page buffer coupled to the bit lines is placed on the other side of the memory cell array.
Recently, in order to further increase the degree of integration of flash memory devices, active research has been carried out on a multi-bit cell which is capable of storing plural data in one memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
Each of flash memory cells of a flash memory device includes a current path, formed between a source and a drain over a semiconductor substrate, and a floating gate and a control gate formed between insulating layers over the semiconductor substrate. Further, the program operation of a flash memory cell is mainly performed by applying a high positive voltage to the control gate so that Fowler-Nordheim (F-N) tunneling is generated between the floating gate and the semiconductor substrate in the state in which the source and drain regions of the memory cell and the substrate (i.e., a bulk region) are grounded. In such F-N tunneling, an electric field of the high voltage applied to the control gate causes electrons of the bulk region to be accumulated in the floating gate, and so the threshold voltage of the memory cell rises.
A nonvolatile memory device has higher reliability when the distribution of threshold voltages of programmed memory cells is narrowed. Accordingly, it is important to narrow the distribution of threshold voltages when performing a program operation. One of the methods used to narrow the distribution of threshold voltages is a double verification method.
FIG. 1A is a diagram showing verification voltages when a double verification operation is performed in the distributions of threshold voltages, and FIG. 1B is a flowchart illustrating a program operation using the double verification operation.
Referring to FIG. 1A, a first threshold voltage distribution 110 includes erase cells, and a second threshold voltage distribution 120 includes program cells. PV1 denotes a first verification voltage, and PV2 denotes a second verification voltage.
A program operation is described below. When data to be programmed and address information input together with a program command are input, a nonvolatile memory device performs a program at step S101 and then performs a first verification operation using the first verification voltage PV1 at step S103. The nonvolatile memory device performs a second verification operation using the second verification voltage PV2 at step S105.
If, as a result of the second verification operation, all memory cells are determined to pass as programmed at step S107, the program is terminated. If, as a result of the second verification operation, however, any one of the memory cells is determined to not have been programmed, the program is performed again. Here, the voltage of a corresponding bit line is changed based on a result of the first verification operation at step S109.
That is, the result of the first verification operation is stored in the latch of the page buffer on a bit-line basis. The voltage of the bit line is changed according to a data status latched in the page buffer. A certain voltage is applied to a bit line that is determined to be a program pass as a result of the first verification operation. 0 V is applied to a bit line that is determined to be a program fail as a result of the first verification operation.
After a voltage is applied to a bit line as described above, a program voltage that is raised by as much as a set step voltage is applied to a word line according to an increment step program pulse (ISPP) method at step S111. Next, the program is performed again.
After the voltage is applied to the bit line, a speed at which a memory cell determined to have passed as programmed in the first verification operation is programmed can be made to be comparatively slow by controlling a program degree of the memory cell for the program voltage. Accordingly, the width of a distribution of threshold voltages of memory cells can be narrowed by controlling the program speed of a memory cell that is rapidly programmed as compared with the program speed of a memory cell that is comparatively slowly programmed.
However, in the double verification operation, the voltage of a bit line is changed depending on whether corresponding memory cells are determined to have passed as programmed for the first verification voltage. The double verification operation may not be used to control the voltage of a bit line more accurately according to a program degree of corresponding memory cells.